/**
 ******************************************************************************
 * @file    system_stm32f2xx.c
 * @author  MCD Application Team
 * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
 *
 *   This file provides two functions and one global variable to be called from
 *   user application:
 *      - SystemInit(): This function is called at startup just after reset and
 *                      before branch to main program. This call is made inside
 *                      the "startup_stm32f2xx.s" file.
 *
 *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be
 *used by the user application to setup the SysTick timer or configure other
 *parameters.
 *
 *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
 *                                 be called whenever the core clock is changed
 *                                 during program execution.
 *
 ******************************************************************************
 * @attention
 *
 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
 *
 * Redistribution and use in source and binary forms, with or without
 *modification, are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright
 *notice, this list of conditions and the following disclaimer in the
 *documentation and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/** @addtogroup CMSIS
 * @{
 */

/** @addtogroup stm32f2xx_system
 * @{
 */

/** @addtogroup STM32F2xx_System_Private_Includes
 * @{
 */

#include "stm32f2xx.h"

#if !defined(HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif                                 /* HSE_VALUE */

#if !defined(HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif                                 /* HSI_VALUE */

/**
 * @}
 */

/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
 * @{
 */

/**
 * @}
 */

/** @addtogroup STM32F2xx_System_Private_Defines
 * @{
 */
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted
     on STM322xG_EVAL board as data memory  */
/* #define DATA_IN_ExtSRAM */

/*!< Uncomment the following line if you need to relocate your vector Table in
     Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET                     \
  0x00 /*!< Vector Table base offset field. \
            This value must be a multiple of 0x200. */
/******************************************************************************/

/**
 * @}
 */

/** @addtogroup STM32F2xx_System_Private_Macros
 * @{
 */

/**
 * @}
 */

/** @addtogroup STM32F2xx_System_Private_Variables
 * @{
 */

/* This variable can be updated in Three ways :
    1) by calling CMSIS function SystemCoreClockUpdate()
    2) by calling HAL API function HAL_RCC_GetHCLKFreq()
    3) each time HAL_RCC_ClockConfig() is called to configure the system clock
   frequency Note: If you use this function to configure the system clock; then
   there is no need to call the 2 first functions listed above, since
   SystemCoreClock variable is updated automatically.
*/
uint32_t SystemCoreClock        = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
/**
 * @}
 */

/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
 * @{
 */

#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */

/**
 * @}
 */

/** @addtogroup STM32F2xx_System_Private_Functions
 * @{
 */

/**
 * @brief  Setup the microcontroller system
 *         Initialize the Embedded Flash Interface, the PLL and update the
 *         SystemFrequency variable.
 * @param  None
 * @retval None
 */
void SystemInit(void) {
  /* Reset the RCC clock configuration to the default reset state ------------*/
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;

  /* Reset CFGR register */
  RCC->CFGR = 0x00000000;

  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;

  /* Reset PLLCFGR register */
  RCC->PLLCFGR = 0x24003010;

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;

  /* Disable all interrupts */
  RCC->CIR = 0x00000000;

  /* enable all gpio clock */
  RCC->AHB1ENR |= 0x000000FF;
#ifdef DATA_IN_ExtSRAM
  SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */

  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}

/**
 * @brief  Update SystemCoreClock variable according to Clock Register Values.
 *         The SystemCoreClock variable contains the core clock (HCLK), it can
 *         be used by the user application to setup the SysTick timer or
 * configure other parameters.
 *
 * @note   Each time the core clock (HCLK) changes, this function must be called
 *         to update SystemCoreClock variable value. Otherwise, any
 * configuration based on this variable will be incorrect.
 *
 * @note   - The system frequency computed by this function is not the real
 *           frequency in the chip. It is calculated based on the predefined
 *           constant and the selected clock source:
 *
 *           - If SYSCLK source is HSI, SystemCoreClock will contain the
 * HSI_VALUE(*)
 *
 *           - If SYSCLK source is HSE, SystemCoreClock will contain the
 * HSE_VALUE(**)
 *
 *           - If SYSCLK source is PLL, SystemCoreClock will contain the
 * HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
 *
 *         (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file
 * (default value 16 MHz) but the real value may vary depending on the
 * variations in voltage and temperature.
 *
 *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file
 * (its value depends on the application requirements), user has to ensure that
 * HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this
 * function may have wrong result.
 *
 *         - The result of this function could be not correct when using
 * fractional value for HSE crystal.
 *
 * @param  None
 * @retval None
 */
void SystemCoreClockUpdate(void) {
  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;

  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & RCC_CFGR_SWS;

  switch (tmp) {
    case 0x00: /* HSI used as system clock source */
      SystemCoreClock = HSI_VALUE;
      break;
    case 0x04: /* HSE used as system clock source */
      SystemCoreClock = HSE_VALUE;
      break;
    case 0x08: /* PLL used as system clock source */

      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
         SYSCLK = PLL_VCO / PLL_P
         */
      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
      pllm      = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;

      if (pllsource != 0) {
        /* HSE used as PLL clock source */
        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
      } else {
        /* HSI used as PLL clock source */
        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
      }

      pllp            = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
      SystemCoreClock = pllvco / pllp;
      break;
    default:
      SystemCoreClock = HSI_VALUE;
      break;
  }
  /* Compute HCLK frequency --------------------------------------------------*/
  /* Get HCLK prescaler */
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  /* HCLK frequency */
  SystemCoreClock >>= tmp;
}

#ifdef DATA_IN_ExtSRAM
/**
 * @brief  Setup the external memory controller.
 *         Called in startup_stm32f2xx.s before jump to main.
 *         This function configures the external SRAM mounted on STM322xG_EVAL
 * board This SRAM will be used as program data memory (including heap and
 * stack).
 * @param  None
 * @retval None
 */
void SystemInit_ExtMemCtl(void) {
  /**
   *   Shared GPIO like A and D
   *   PE[00..01]  = NBL[00..01]
   *   PE[03..06]  =   A[19..22]
   *   PE[07..15]  =   D[04..12]
   *   PF[00..05]  =   A[00..05]
   *   PF[12..15]  =   A[06..09]
   *   PG[00..05]  =   A[10..15]
   *   PG6         =   FSMC_INT2
   *   PG7         =   LCD_FMARK
   *   PG8         =   LCD_BL
   *   PG9         =   FSMC_NE2
   *   PG10        =   FSMC_NE3
   *   PG12        =   FSMC_NE4
   *   PD[8-13]    =   D[13-18]
   *   PD14-15]    =   D[0-1]
   *   PD[0-1]     =   D[0-1]
   *   PD4         =   FSMC_NOE
   *   PD5         =   FSMC_NWE
   *   PD6         =   FSMC_NWAIT
   *   PD7         =   FSMC_NCE2
   *
   *   IS61WV102416BLL 2MB
   */

  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
  // RCC->AHB1ENR = 0x00000078;

  /**
   * Connect PDx pins to FSMC Alternate function
   * alternate 12 is fsmc
   */
  GPIOD->AFR[0] = 0xcccc00cc;
  GPIOD->AFR[1] = 0xcccccccc;
  /**
   *  Configure PDx pins in Alternate function mode
   *  afe 2
   */
  GPIOD->MODER = 0xaaaaaa0a;
  /**
   *  Configure PDx pins speed to 100 MHz
   *  heigh speed 3
   */
  GPIOD->OSPEEDR = 0xffffff0f;
  /* Configure PDx pins Output type to push-pull */
  GPIOD->OTYPER = 0x00000000;
  /* No pull-up, pull-down for PDx pins */
  GPIOD->PUPDR = 0x00000000;

  /* Connect PEx pins to FSMC Alternate function */
  GPIOE->AFR[0] = 0xccccc0cc;
  GPIOE->AFR[1] = 0xcccccccc;
  /* Configure PEx pins in Alternate function mode */
  GPIOE->MODER = 0xaaaaaa8a;
  /* Configure PEx pins speed to 100 MHz */
  GPIOE->OSPEEDR = 0xffffffcf;
  /* Configure PEx pins Output type to push-pull */
  GPIOE->OTYPER = 0x00000000;
  /* No pull-up, pull-down for PEx pins */
  GPIOE->PUPDR = 0x00000000;

  /* Connect PFx pins to FSMC Alternate function */
  GPIOF->AFR[0] = 0x00cccccc;
  GPIOF->AFR[1] = 0xcccc0000;
  /* Configure PFx pins in Alternate function mode */
  GPIOF->MODER = 0xaa000aaa;
  /* Configure PFx pins speed to 100 MHz */
  GPIOF->OSPEEDR = 0xff000fff;
  /* Configure PFx pins Output type to push-pull */
  GPIOF->OTYPER = 0x00000000;
  /* No pull-up, pull-down for PFx pins */
  GPIOF->PUPDR = 0x00000000;

  /* Connect PGx pins to FSMC Alternate function */
  GPIOG->AFR[0] = 0x0ccccccc;
  GPIOG->AFR[1] = 0x000c0cc0;
  /* Configure PGx pins in Alternate function mode */
  GPIOG->MODER = 0x02282aaa;
  /* Configure PGx pins speed to 100 MHz */
  GPIOG->OSPEEDR = 0x033c3fff;
  /* Configure PGx pins Output type to push-pull */
  GPIOG->OTYPER = 0x00000000;
  /* No pull-up, pull-down for PGx pins */
  GPIOG->PUPDR = 0x00000000;

  /*-- FSMC Configuration
   * ------------------------------------------------------*/
  /* Enable the FSMC interface clock */
  RCC->AHB3ENR = 0x00000001;

  /* Configure and enable Bank1_SRAM3 */
  /* BCR  */
  FSMC_Bank1->BTCR[4] = FSMC_BCR3_WREN + FSMC_BCR3_MWID_0 + FSMC_BCR3_MBKEN;
  /* BTR  */
  FSMC_Bank1->BTCR[5] = (1 << FSMC_BTR3_BUSTURN_Pos) + (1 << FSMC_BTR3_ADDHLD_Pos) + (1 << FSMC_BTR3_ADDSET_Pos);

  /* not used for write time config */
  FSMC_Bank1E->BWTR[4] = 0x0fffffff;

  /* Configure and enable Bank1_SRAM4 */
  /* BCR  */
  FSMC_Bank1->BTCR[6] = FSMC_BCR4_WREN + FSMC_BCR4_MWID_0 + FSMC_BCR4_MBKEN;
  /* BTR  */
  FSMC_Bank1->BTCR[7] = (1 << FSMC_BTR4_BUSTURN_Pos) + (15 << FSMC_BTR4_ADDHLD_Pos) + (0 << FSMC_BTR4_ADDSET_Pos);

  /* not used for write time config */
  FSMC_Bank1E->BWTR[6] = 0x0fffffff;
}
#endif /* DATA_IN_ExtSRAM */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
